Demand automated computer

ABSTRACT

A computer and controls system which monitors the application of power or other quantities subject to demand in which increased costs results due to periodic periods of high demand and controls loads on the system so that the cost is minimized while maintaining the desired service. This invention also allows continuous demand monitoring on industrial processes which are necessary for a specific application.

United States Patent Dillon et al. [451 Mar. 28, 1972 541 DEMAND AUTOMATED COMPUTER 3,522,421 8/1970 Miller ..23s/151.21 72 Inventors: Vearl Joseph Dillon, Chicago; Walter M. 3'296'452 235/ 15 x Threewm Carpentersvine both on 3,517,168 6/1970 Gates at al. ..235/151.21 X 3,517,310 6/1970 Gates et a1. ..235/151.21 X [73] Assignee: Edac Company, Chicago, Ill. [22] Filed: Man 2, 1970 Primary Examiner-Malcolm A. Nlorrison Assistant Examiner-Edward J. Wise 1 1 PP 15,348 Attorney-Hill, Sherman, Meroni, Gross & Simpson 52 us. 01 ..235/l51.31, 235/15121 [571 ABSTRACT [51] Int. Cl 1 G06! 15/56 A computer and controls system which monitors the applica [58] Field of Search ..235/1S1.31, 151.21, 183; on of power or other quantities Subject to demand in which 307/31 35 increased costs results due to periodic periods of high demand 5 6 R f cited and controls loads on the system so that the cost is minimized 1 e erences while maintaining the desired service. This invention also al- UNTED STATES PATENTS lows continuous demand monitoring on industrial processes which are necessary for a specific application. 3,539,785 11/1970 Baker ..235/l83 X 3,387,121 6/1968 Maczuzak et a1 ..235/l51.21 3 Claims, 31 Drawing Figures TIME BASE GENERATOR TRIGGER CONTROL 8 GATING UNIT STORAGE AD DRESS COU NTER CURRENT RATE REGISTER MEMORY ELEMENT UP DATE REGISTER VARIABLE COMPARATOR TO LOADS PATENTED R2 I912 3,652,838

SHEET 010! 20 POWER DEMAND DEMAND= Fig. I

POWER (KW) DE MAN D 2nd INTERVAL DE MAND lsf INTERVAL Tl'TtFlSf DEMAND INTERVAL T2- T|= 2nd DEMAND INTERVAL Tn-Tm-|)=nth DEMAND INTERVAL Fig.2

D I NVENTUR S l/ear/ (/0512 i2 017/0 Ma/fer M 7 ream n71 aw (./WA'HURN/iY-S Fig. 3

POWER POWER (KW) (KW) v PRESET PRESET DEMAND DEMAND POINT POINT &

ACTUAL- D DEMAND ACTUAL DEMAND no ENE TIME 40 T|To =DEMANDTIME INTERVAL 4b INVUNI'URS l/ear/ dosiqo/z 0/7/0/7 h a/ler M fireeW/f PATENTEDMARZE; I972 3, 52 8 3 SHEET C2 0F 20 INCOMING EILECTRIC Qfi CE PRIOR ART LOGIC --TRANSDUCER f UNn I 'i IV I l I l I v I l I NON-DEFERRABLE I ELECTRIC LOADS DEFERRABLE ELECTRIC LOADS PATENTinmzemz 3,652,838

SHEEI 03 0F '20 POWER DEMAND (KW) mw) PRESET 555% DEMAND (I200) A (|200) v 90o ifi ACTUAL DEMAND DEMAND 0 IO 20 3o 0 f0 20 20 TIME (MIN) TIME (MIN) F i g. 50 V Fig. 5b

OPERATIONAL DEMAND BAND(TYF?) W TIME -0 Fig. 60 Fig. 6b Fig. 6c Fig. 6d

INV/iNI'URS Vear/ 1/089 6 0/7/0/7 [Va/fer M 7' reew/Y/ PATENTEnmzsmz 3,652,838

SHEET cu 0F 20 POWER ACTUAL DEMAND FOR |5TO45 MIN- 600 INTERVAL 2oo l 0 f5 3'0 4'5 60 Fig-7 MANUFACTURED L MANUFACTURED CYCLE CYCLE REVENUE CYCLE DEMAND J Fig 8 0 1'5 30 1% 6O TIME(MIN.)

I N VENTURS' Vear/ Mose /7 0/7/00 Wa/fel' M breez /72 @zWmvmmws PATENTEIIIIIR28 I972 3, 652.838

SHEET 05 [1F 20 POWER (Kw) N I i a S Y-N At f TIME I N FIXED DEMAND TIME INTERVAL. DEMAND-i pm PRESENT TIME WHEN DEMAND IS coMnARED TO (MEASURED PM PRESET DEMAND. CONT'NUOSLY IN= BEGINNING OF FIXED TIME INTERVAL.

P(f)= QUANTITY BEING MEASURED AS A FUNCTION OF TIME.

Fig. 9

l ear/ dose f) 0/7/01? PVa/r'er M Uneas /7;

PATENTEIIIIIRza N2 3,652,838

saw B 0F POWER (KW) DEFERRABLE LOAD TIME IHR. 3OMIN.

IIoo

Ioo-- I I E o so 90 I20 I I TIME Fig. I00

DEMAND DEFERRAB E I oAD TIME IHR. 30 MIN.

TIME Fig. IOb

DEMAND DEFERRABLE LOAD TIME l2 MIN.

l NVEATU/(S Vear/ dose /2 0/7/01; lVa/far/Z fire eW/I I 86 f 'krmmwws SHEET 0711f 20' DEMAND DIFFERENTIAL (Kw)BANDw|DTH 2QQ\I8 DEMAND (KW) 0o0-oooo0oooo-*2l CONTROL BYPASS Fig. ll

PATENTEDMAm m2 (UPPER) DEMAND PRESET! (LOWER) OFF CONTROLLED ELECTRICAL LOADS DEMAND PRES INVli/\"l (ms l ear/ z/ose o/z 0/7/00 fi a/fer Al, i'firee W/V/ @Wwvmwuw PATENTEDIIAR28 i972 3, 652.838

SHEET 09 0F 20 22 23 60 Hz AT STORAGE TIME BASE GENERATOR C%%?I T R cRR CLEAR 24 AT FULL CURRENT CRRP RATE ADDRESS WRITE REGISTER LINES 34 I 00 IOO KC HSE UNT 2 osc TR'GGER NABLE 33 CONTROL READ/W H: MEMORY & GATING ENABLE ELEMENT SAMPLE C P UN|T PG VOLTAGE I 27 (L LREAI) 5 :I' 8 URP UPDATE 5n E FULL ER LINES 8 I 520" 28 SIO AOCUMULATOR s VARIABLE I, RATE REG'STER Li; COMPARATOR 0oMPuTE 29 [INHIBIT PROGRAMING DRCP' LOAD DECODER PICKUP CONTROL JTO LOADS Fig. l3

4 INVENTURS Vear/ Jase h 0/7/0/7 h a/ferfl fires 207,71

BY w; WAT/always PATENTEDMAR28 I972 3,652,838

SHEET 10 0F 20 TIME DELAY GENERATOR 32 PAST 38 5O SAMPL PG w ggL mT I u VOLTAGE CURRENT PULSE 1. DOWN lgp ACCUMULATOR 36 .REGISTER DATA LINES PROGRAMING 3O DECODER DROP PICKUP r 29 co Tv Te zaL LOADS Fig. l4

Vea r/ Muse /2 10/7/01) 1%7/fer/M ZfieQW/V/ PATEmEnmzslevz 3,652.838

SHEET 11UF2O 5 CURRENT RATE PULSE OUTPUT(CRP) SAMPLE VOLTAGE INPUT Fig. l5

' [NV/ZN! (m5 Ksar/ dose oh 0/7/00 Wa/fer M 777reew/7/ g. A'IVURNUYS m %W W pg B35511 WRITE s2 PULSE HEAD 306 ERASE gS C HEAD 46 READ PAST HEAD PULSE I 38 6 64 ACC PULSE o CQUNT DOWN S O---- l D coum uP 62 Fig. l6

' INVENT'URS Vear/ a/osie o/ 0/// 0/7 [Va/fer M firewvf 'PATENTEnMme I972 3,652,838

SHEET 16 0F 20 READ WRITE ENABLE CRR PULSE URacRR CL COMPUTE INHIBIT ENABLE Fig. 20

UR FULL ACC FULL CRP INVENTORS K942 r/ dose 0/7/0/9 l Va/fer/f, fireezw/i BY QLf W aw; @Wrmmvms PATENTED MR 2 8 m2 SHEET 180F210 mom mwzj mmwmo Gum-DOME m mmnzza 3 mow INVENTORS l ear/ close of; 0/7/01) Wa/fer M Three w/kz ay g @WTTORNEYS 

1. A demand computer for continuously accumulating a quantity over a fixed time interval and said interval being divided into a fixed number of lesser time intervals designated delta T increments and said fixed time interval having starting and ending delta T increments which are continuously changing as the fixed time interval moves through time, comprising: a pulse generator means receiving a variable voltage indicative of the quantity and converting it into pulses whose frequency is indicative of the rate of usage of said quantity; a time base generator means for converting 60 cycle timing signals into short term timing intervals designated delta T increments; means for counting said delta T increments to define a demand period as a fixed number of delta T increments receiving an input from said time base generator; an accumulator means for storing the integral of said quantity which can be continuously altered by removing pulses representative of the rate of usage of said quantity during an update timing period or acquire pulses representative of the rate of usage of said quantity during an alternate compute timing period, said accumulator having contents at any moment in time equal to the sum of all pulses generated by the pulse generator over the demand period from the present delta T increment through the past fixed number of delta T increments defining the demand period; a current rate register means for storing the number of pulses developed by the pulse generator in one delta T increment and capable of holding the maximum expected number of pulses until a new delta T increment begins; a memory element composed of solid state memory devices divided into discrete storage addresses, each address of which is capable of storing the maximum value that can be acquired by the current rate register; means for entering into the enabled address of the memory element on a write command the data stored in the current rate register and means for removing from the memory element on a read command the data stored in said memory element from the address which is enabled and means for storing said data removed from said memory element in an update register; a storage address counter means for counting the delta T increments such that a full count is equal to the fixed number of delta T increments in a demand period and means for decoding the count in the storage address counter for enabling one discrete address in the memory element for each count value in the storage address counter; an update register means for receiving data stored in the memory element equal to the amount acquired in one delta T increment and having been stored in the memory element for the length of one demand period minus one delta T increment and having means to decode a full state and generate a control gate to control pulses to the accumulator register; a trigger control and gating means receiving the output of said pulse generator and supplying an input to said accumulator, said current rate register and said update register, and including means for generating read and write commands to control said memory element and further including means for generating timing cycles for compute and update functions as required to maintain a continuous integral in said accumulator register; a programming decoder means monitoring the contents of said accumulator and initiating a control command when said contents exceed a preset limit and also containing means for presetting an offset value lower than the preset limit which will initiate a pickup control command when the contents of said accumulator drop below the preset limit minus the offset value; and a load controller means connected to said programming decoder for receiving pickup and drop commands from said programming decoder and sequentiallY transferring said commands into open or closed relay contacts to control peripheral equipment.
 2. A demand computer according to claim 1 wherein said accumulator means includes decoding means for continuously decoding the binary contents of said accumulator to provide a decimal output.
 3. A demand computer according to claim 1 further including a variable rate comparator receiving inputs from said pulse generator, said memory element and said time base generator, and supplying an output to said trigger control and gating means. 